Dholera First Wafer Out Marks India Entering the Era of Domestic Chip Manufacturing
Tata Electronics has announced the achievement of first wafer out at the Dholera semiconductor fabrication plant, the milestone that marks the transition from process development and equipment qualification to commercial manufacturing operations. First wafer out, the moment when the first batch of wafers completes the full process flow and exits the fab as finished product, is the most watched event in the life of any new semiconductor manufacturing facility. It confirms that every piece of installed equipment is qualified and working within specification, that the process integration between deposition, lithography, etch, and metrology steps is correct, and that the facility's quality management systems are functioning as designed. The Dholera first wafer out carries particular weight because it is the first time this sequence has been completed at a wafer fabrication plant on Indian soil in the modern semiconductor era.
Process Qualification Journey and PSMC Partnership
The Tata Electronics Dholera fab is built around the 28nm process technology transferred from PSMC, the Taiwanese foundry that is Tata's technology partner for the facility. Process qualification for a new fab involves running a series of test wafer splits through every process module, characterising the electrical performance of transistors and passive devices fabricated in each split, and comparing the results against the process target specifications that PSMC uses at its own fabs in Taiwan. When all process modules are qualified to specification individually, the full integration flow is run and the electrical test results for the complete chip are compared against the qualified process baseline. The Dholera facility passed all qualification splits over the preceding months, and the first wafer out represents completion of the final full-flow integration run. PSMC process engineers who supported the qualification phase from both Dholera and Taiwan expressed confidence that the facility's process parameters are well-centred and that yield improvement to commercial targets is achievable within the planned ramp schedule.
Equipment Fleet and Fab Infrastructure
The Dholera fab's equipment fleet, assembled over two years of procurement and installation, includes lithography scanners from ASML, etch and deposition systems from Applied Materials and Lam Research, process control equipment from KLA, and chemical mechanical planarisation tools from Applied Materials. The installation and qualification of each equipment type required collaboration between the equipment manufacturer's field engineers and Tata's process integration team, with Japanese materials companies JSR and Fujifilm providing the photoresist, anti-reflective coating, and CMP slurry formulations qualified for the process. The cumulative investment in equipment and infrastructure at Dholera represents the largest single capital commitment to manufacturing in India in the current decade, and the first wafer out validates that this capital has been correctly deployed to build a functioning semiconductor manufacturing facility.
Path to Commercial Volume and Customer Readiness
Following first wafer out, the Dholera fab will enter its yield ramp phase, during which the process team works to improve the ratio of functional chips to total chips fabricated by identifying and eliminating defect sources. The yield at first wafer out is typically well below commercial targets, and a structured improvement programme using the yield management tools installed from KLA and the process control algorithms developed by the facility's engineering team will drive yield upward over the following quarters. Customer qualification lots for the initial design wins, including chips from fabless customers that were engaged during the ISM-enabled customer acquisition process, will be run in parallel with the yield ramp programme. The first commercial customer shipments from Dholera are targeted for Q1 2027, making India a wafer foundry location for the first time in its semiconductor history.
