Semicon 2.0 Launches Plan to Train One Lakh Chip Engineers by 2030

India Launches Ambitious Plan to Build a Semiconductor Engineering Workforce

The talent development pillar of India's Semicon 2.0 programme, part of the INR 1.27 lakh crore scheme notified by MeitY in August 2026, has moved into implementation with the announcement of detailed plans to train one lakh chip engineers by 2030. The programme addresses what the government and industry have jointly identified as the most critical constraint on India's semiconductor ambitions: not capital, not policy, and not land, but the availability of engineers with specific chip design, process engineering, and test engineering skills who can populate the design centres, OSAT facilities, and eventually the wafer fab that India's investments are creating. The talent pillar represents an acknowledgment that building the physical infrastructure without building the human capital to operate it is an incomplete strategy.

Academic Programme Reforms and Industry Integration

The Semicon 2.0 talent plan involves curriculum reforms at IITs and NITs to introduce dedicated semiconductor engineering tracks at the undergraduate level, covering VLSI design, semiconductor physics, process technology, and electronic design automation tools. Fifty technical universities and colleges across India will receive support to establish semiconductor specialisation programmes, with laboratory infrastructure funded partly through the scheme and partly through industry contributions. A system of industry-funded semiconductor design chairs at academic institutions will bring practising chip engineers from companies including Qualcomm, AMD, Intel, and domestic startups into teaching roles, bridging the gap between theoretical curricula and the practical skills that industry requires. The design chairs programme is modelled on similar arrangements in Taiwan and South Korea that have proven effective at accelerating the development of industry-relevant engineering talent.

Internship and Apprenticeship Pipeline

A national chip design internship programme will connect engineering students from the second year onwards with semiconductor companies for structured learning placements. Companies participating in the programme receive a per-intern support payment from the government, reducing the cost of running internship programmes and incentivising companies to take on larger cohorts. A separate apprenticeship track targets technical diploma holders and ITI graduates for operator and technician roles in OSAT facilities, recognising that the 50,000-plus manufacturing workforce being recruited by Tata Electronics, Kaynes, CG Power, and Micron requires a different educational pathway than chip design engineers. The combination of the two tracks is designed to develop the full human capital stack that a mature semiconductor manufacturing ecosystem requires, from fab operators to CPU architects.

Measuring Progress and the 2030 Target

The one lakh engineer target by 2030 is ambitious in the context of India's current semiconductor engineering pipeline. Estimates of the current chip design engineer pool in India range from 25,000 to 40,000, depending on how broadly the category is defined. Reaching one lakh requires more than doubling to tripling the supply of qualified engineers in four years, which the programme's planners believe is achievable given the large number of electronics engineering graduates from Indian universities who currently enter IT services rather than semiconductor careers. Converting even a portion of this pool through reskilling programmes and making semiconductor career paths more visible and appealing is seen as a realistic pathway to the target, though execution quality across dozens of institutions will determine whether the aspiration translates into practice.