Semicon 2.0 Offers 40 Percent Capital Subsidy for New Semiconductor Fabs

Semicon 2.0 Sets Fab Subsidy at 40 Percent and Defines Investment Thresholds by Segment

India's Semicon 2.0 programme has formalised the incentive structures and investment thresholds for each category of semiconductor facility eligible for government support. The gazette notification issued on August 31, 2026 specifies that new front-end semiconductor fabrication facilities, commonly called fabs, will be eligible for a capital expenditure subsidy of up to 40 percent of eligible project cost, with the total subsidy quantum determined by the technology node, planned capacity, and the strategic importance of the product portfolio to be manufactured. The 40 percent subsidy level is designed to bridge the economic gap between India's infrastructure costs and those of incumbent fab locations in Taiwan, South Korea, and China.

Incentive Rates by Facility Category

The Semicon 2.0 notification establishes differentiated subsidy rates across the semiconductor value chain. Front-end wafer fabrication facilities receive a maximum 40 percent capital subsidy, reflecting the enormous capital requirements and long payback periods of logic and memory fabs. Assembly, testing, marking, and packaging facilities, including OSAT and ATMP plants, are eligible for up to 50 percent subsidy, a higher rate that reflects the smaller absolute investment sizes in this segment and the government's priority to rapidly build domestic packaging capacity across multiple sites. Compound semiconductor facilities, covering silicon carbide, gallium nitride, indium phosphide, and other III-V materials, have separate and in some cases more generous thresholds reflecting their strategic importance for defence, power electronics, and telecommunications applications.

Technology Node and Capacity Requirements

Eligibility for the fab subsidy is conditioned on meeting minimum technology node requirements and planned capacity commitments. For front-end silicon fabs, the programme requires participation at 40nm or finer for the maximum subsidy tier, with mature node fabs at 65nm to 110nm qualifying for a lower subsidy tier. Applicants must also commit to minimum monthly wafer capacity thresholds and submit detailed five-year production ramp plans reviewed by the ISM technical committee. These requirements ensure that Semicon 2.0 fab support goes to genuine manufacturing projects with credible operational plans rather than speculative real estate or infrastructure plays dressed as semiconductor projects.

State Government Co-Investment Framework

Semicon 2.0 maintains the cost-sharing model pioneered under Semicon 1.0, under which state governments contribute land, infrastructure, water, power, and additional financial incentives to complement the central government's capital subsidy. States including Gujarat, Telangana, Karnataka, Maharashtra, Odisha, and Uttar Pradesh have all signalled their intent to aggressively court Semicon 2.0 applicants with competitive state-level packages. The central-state co-investment model distributes fiscal risk while ensuring that fab projects are located in states with the infrastructure commitment and administrative capability to support complex semiconductor manufacturing operations over multi-decade facility lifetimes.

Implications for the Next Wave of Indian Fabs

With the Tata-PSMC Dholera fab nearing completion and first silicon expected in December 2026, the Semicon 2.0 subsidy framework is designed to catalyse a second and third fab project in India before the end of the decade. ISM CEO has stated that India aspires to have 10 semiconductor fabs over the long term, and the Semicon 2.0 financial framework is intended to make that ambition economically viable by significantly reducing the effective capital cost for any company willing to build in India. Equipment vendors, EDA companies, and materials suppliers attending SEMICON India 2026 are expected to announce India-specific partnership and localisation plans aligned with the new policy framework.