Semicon Hunt -> technology -> India Semiconductor Mission / MeitY
2026-11-02
The India Semiconductor Mission has launched the second phase of its Semcon 2.0 semiconductor talent development programme, committing INR 3,200 crore to train one lakh chip engineers over four years across a network of 60 university and polytechnic institutions. Phase two adds VLSI physical design, analog circuit design, and semiconductor process engineering curricula absent from the first phase, and introduces a stipend-based industry internship component requiring each trainee to complete six months at an approved semiconductor company before certification.
The India Semiconductor Mission has announced the launch of Semcon 2.0 Phase Two, a substantially expanded semiconductor talent development programme that commits INR 3,200 crore over four years to train one lakh chip engineers across a network of 60 institutions. Phase two builds on the first phase's foundation of digital design and EDA tool training by adding three critical curriculum tracks that the first phase did not cover: VLSI physical design covering place and route, timing closure, and chip finishing for advanced nodes; analog and mixed-signal circuit design covering op-amp design, data converter architectures, and RF circuit fundamentals; and semiconductor process engineering covering wafer fabrication unit processes, metrology, and yield management. The addition of these tracks addresses the specific talent gaps that semiconductor companies operating in India have identified as the most significant constraint on expanding their India engineering operations.
The 60 institutions in the Phase Two network include IITs, NITs, central universities, and for the first time, polytechnic institutions that will offer shorter-duration certificate programmes targeting technician-level roles in semiconductor manufacturing. The curriculum standards for each track have been developed jointly by ISM's academic advisory committee and industry working groups convened by SEMI India, ensuring that the content reflects current industry practice rather than outdated textbook material. EDA tool vendors including Cadence and Synopsys are providing academic licence programmes that give all 60 institutions access to industry-standard tools at no cost, removing the infrastructure barrier that has historically prevented many Indian universities from teaching practical chip design. The curriculum will be reviewed and updated annually to track the evolution of process technology and design methodology, with ISM funding annual refresh workshops for faculty at all network institutions.
The mandatory six-month industry internship component is the most significant structural innovation in Phase Two relative to the first phase. Each Semcon 2.0 trainee must complete a qualifying internship at an ISM-approved semiconductor company before receiving certification, creating a direct connection between training and employment. ISM has established a central placement portal that matches trainees with internship slots at approved companies, covering design houses, OSAT facilities, equipment companies, EDA firms, and semiconductor design services providers. Approved companies receive an ISM subsidy of INR 15,000 per month per intern to offset the cost of supervision and onboarding, making the programme economically accessible to smaller companies that might otherwise be unable to absorb intern cohorts. The internship model is expected to dramatically improve the employment rate of Semcon graduates relative to purely classroom-based training by ensuring that every certified engineer has demonstrated industry-relevant skills in an actual workplace setting.
ISM's target outcome for the full four-year Phase Two programme is the certification of one lakh engineers, of whom a majority are expected to take up roles in the semiconductor sector within one year of certification. The programme is specifically designed to support the staffing needs of the Tata Dholera fab, the CG Power and Micron Sanand OSAT facilities, and the expanding design centre operations of US and Japanese semiconductor companies in Bengaluru, Hyderabad, Chennai, and Pune. Industry reactions to the Phase Two launch have been strongly positive, with companies noting that the inclusion of physical design and process engineering tracks finally addresses the categories of talent that are most difficult to hire from general engineering graduates and where India's current gap relative to Taiwan and South Korea is widest. SEMI India has formally endorsed the programme and committed its member companies to providing 5,000 internship slots in the first year.
The form has been successfully submitted.
We will review your software soon!
See you soon.
Please enter your details and we will