Imec-IISc Programme Places India in the Global Frontier of Semiconductor Process Research
Imec, the Belgian nanoelectronics and digital technology research centre that is globally regarded as the foremost independent semiconductor process research institution, has jointly launched a multi-year research programme with the Indian Institute of Science covering semiconductor process nodes below 5nm. The programme, funded jointly by Imec, IISc, and India's Department of Science and Technology, addresses three of the most challenging technology areas in the current semiconductor roadmap: gate-all-around transistor integration, which replaces the FinFET transistor structure used at current leading-edge nodes with a new architecture that provides superior electrostatic control at gate lengths below 7nm; extreme ultraviolet lithography patterning, covering the resist, underlayer, and computational lithography techniques required to print features at sub-5nm dimensions; and 3D chip stacking using hybrid bonding, which enables the face-to-face bonding of chiplets at connection pitches below one micron. With this programme, India joins the small group of countries that have active research programmes on semiconductor technology nodes that are years away from commercial production.
Gate-All-Around Technology and the Post-FinFET Era
Gate-all-around transistors, the device structure that TSMC, Samsung, and Intel have all chosen for their sub-5nm technology generations beyond FinFET, represent a fundamental change in how the transistor gate wraps around the current-carrying channel. In a FinFET, the gate contacts three sides of a fin-shaped silicon channel. In a gate-all-around device, the channel is a nanowire or nanosheet with the gate material surrounding it on all four sides, providing much stronger electrostatic control that suppresses current leakage at shorter channel lengths. Fabricating gate-all-around devices requires new epitaxial deposition processes, new etch selectivities between materials that must be removed on some surfaces while being preserved on others, and new stress engineering techniques to maintain carrier mobility in the confined nanosheet geometry. The Imec-IISc research programme investigates these process challenges at the research laboratory scale, developing the fundamental understanding that will eventually inform commercial process development at foundries.
EUV Patterning and Resist Science
Extreme ultraviolet lithography, using 13.5nm wavelength light to pattern features at sub-10nm dimensions, is the lithography technology that enables the most advanced semiconductor process nodes. EUV lithography requires photoresists that respond to EUV photons with high contrast and low roughness, anti-reflective underlayers that suppress standing wave effects, and computational lithography algorithms that correct for optical proximity effects and mask absorber physics specific to EUV. The Imec-IISc EUV patterning research focuses on two areas where fundamental materials science limits current performance: metal oxide photoresist formulations that offer higher EUV absorptance and lower stochastic roughness than current polymer resists, and high-numerical-aperture EUV optical proximity correction models that accurately predict printed feature dimensions at the extreme end of EUV resolution. India does not currently have an EUV scanner, so the experimental patterning work will be conducted at Imec's Leuven facility during researcher exchange visits, with modelling and materials characterisation performed at IISc.
PhD Training and India's Advanced Process Research Capability
The programme's commitment to training 50 PhD students per cohort in advanced semiconductor process research is a significant contribution to India's next-generation semiconductor workforce. India currently has a very small number of researchers with hands-on experimental expertise in sub-10nm process technology, a consequence of the country's historical absence from wafer fabrication. The Imec-IISc PhD cohorts will gain experimental experience at Imec's state-of-the-art facilities in Leuven, developing skills that are essentially unavailable through any domestic Indian programme. These researchers will populate India's growing semiconductor company landscape as process integration engineers, new product introduction specialists, and academic faculty, gradually building the domestic expertise in advanced process technology that will be needed when India's semiconductor ambitions extend beyond current mature-node manufacturing to more advanced nodes in the 2030s.
