IIT Madras's First Chip Cohort Proves India Can Train Students Who Build Real Silicon
IIT Madras's Semiconductor Research Centre has graduated its first chip design cohort, reporting the successful tape-out of six student-designed chips to a commercial foundry through the Efabless fabrication access programme using the SkyWater SKY130 open-source process design kit. The six designs span a range of application domains and circuit disciplines, providing a representative sample of the breadth of chip design expertise being developed at the centre. The cohort includes a neuromorphic processor implementing spike-based neural network computation in analog-digital mixed-signal circuitry, a RISC-V IoT SoC integrating a 32-bit processor core with analogue peripherals and a sub-GHz radio interface, and four analogue sensor front-end chips covering biosignal amplification, capacitive MEMS readout, photodetector transimpedance amplification, and a precision current reference. Each design was completed by a student team of two to four members over a twelve-month programme that took them from architectural specification through RTL design, physical implementation, and design rule check sign-off to tape-out submission.
The Student Chip Programme Model and Efabless Access
The IIT Madras programme uses the Efabless platform, which provides access to the SkyWater SKY130 130nm open-source PDK and a fabrication shuttle that groups multiple small designs onto a shared wafer to reduce the per-design fabrication cost to levels that are accessible for university programmes. The open-source PDK, which includes fully characterised standard cell libraries, SRAM compilers, and analogue device models, allows students to perform complete physical design without the IP access restrictions that commercial PDKs impose, giving them hands-on experience with every step of the design implementation flow. The twelve-month timeline from architecture to tape-out is intentionally challenging, requiring students to make design tradeoffs under schedule pressure in the same way that industry designers work, rather than conducting research that ends at simulation without a commitment to real silicon. When fabricated chips return from the foundry, students test them against their pre-silicon simulations, completing the verification loop and gaining the experience of debugging real silicon behaviour against design intent.
Neuromorphic and RISC-V Designs: Technical Context
The neuromorphic processor designed by the IIT Madras cohort implements a spiking neural network architecture in which neurons communicate through discrete voltage pulses rather than continuous activation values. This approach, inspired by biological brain computation, offers theoretical energy efficiency advantages over conventional deep neural network inference for tasks like gesture recognition, keyword spotting, and biosignal classification, and is an active research area at institutions including Intel, IBM, and leading universities worldwide. The RISC-V IoT SoC design builds on the open-source RISC-V instruction set architecture, which has been adopted by the India semiconductor community as a preferred base for domestic microprocessor development. The IIT Madras SoC integrates a standard RISC-V core with India-designed analogue peripherals and a sub-GHz radio transceiver, creating a complete connected sensor node on a single chip that demonstrates the integration capability of the student team.
Programme Impact and Scale Plans
The first cohort's successful tape-out demonstrates that the IIT Madras Semiconductor Research Centre's programme model works and provides a reference for other Indian institutions establishing chip design programmes. IIT Madras plans to scale the programme to three cohorts per year with twelve designs per cohort by 2028, and is exploring access to more advanced process nodes through partnerships with commercial foundries that offer academic shuttle programmes at 65nm and 40nm. The Centre is also developing a curriculum sharing programme that will allow other Indian universities to adopt the IIT Madras course materials and programme structure, creating a multiplier effect on India's student chip design capacity. Graduates of the programme who have completed a real chip tape-out are significantly more employable at semiconductor companies than those with only simulation experience, and the programme is seen by industry as a model for producing job-ready chip design engineers at scale.
