Calligo CT100 First Silicon Puts India's Security Chip Startup Ambitions to the Test
Calligo Technologies, the Bengaluru-based fabless semiconductor startup specialising in hardware security silicon, has received the first silicon wafers from the foundry for its CT100 RISC-V secure processor chip, entering the post-silicon bring-up and characterisation phase that will determine whether the design performs as modelled and can be advanced to customer sampling. The CT100 is designed for hardware security module and trusted execution environment applications, serving IoT device security, banking terminal authentication, industrial controller security, and the DRDO-funded military secure communications programme for which Calligo was recently awarded a development contract. The chip is fabricated on a 28nm process node and integrates a custom RISC-V processor core with a physical unclonable function circuit for cryptographic key derivation, a true random number generator for entropy provision, and a hardware AES-256 encryption accelerator that delivers cryptographic operations at speeds that software implementations on general-purpose processors cannot match.
RISC-V Security Architecture and Design Choices
The CT100's use of a custom RISC-V processor core rather than a licensed ARM core is a deliberate design and commercial strategy choice by Calligo. RISC-V's open-source instruction set architecture eliminates the recurring royalty payments that ARM-based designs incur, reducing the per-unit cost structure of the CT100 in high-volume IoT applications where chip cost is a primary selection criterion. More importantly for security applications, the open-source nature of RISC-V allows Calligo to implement custom instruction set extensions that accelerate security-specific operations without exposing the processor's security model to the third-party audit requirements that proprietary instruction sets would demand. The physical unclonable function circuit, which generates a unique identifier for each chip from the nanoscale manufacturing variations in the silicon that are unpredictable even to the manufacturer, is implemented as a ring-oscillator PUF that leverages the 28nm process's well-characterised transistor variation statistics to achieve strong statistical uniqueness across the chip population.
Post-Silicon Bring-Up Process and Testing Plan
Post-silicon bring-up involves a structured sequence of tests that progressively confirm the functionality of the CT100's circuit blocks, starting from basic power-on and clock integrity verification through processor execution testing, memory interface validation, cryptographic function characterisation, and PUF uniqueness and reproducibility measurement. Calligo's engineering team is executing this sequence using a combination of custom test fixtures built for the CT100 package format, off-the-shelf JTAG debug tools adapted for the RISC-V debug interface, and a suite of cryptographic test vectors that exercises the AES accelerator and PUF across the temperature range and supply voltage corners specified in the CT100 datasheet. Any deviations from pre-silicon simulation that emerge during bring-up are analysed using the waveform captures and silicon register readback capability of the JTAG interface to identify the design block responsible, guiding the decision of whether the deviation is a silicon bug requiring a chip revision or an artefact of test methodology that can be resolved without new silicon.
Customer Pipeline and Market Context
Calligo has a pipeline of customer engagements across three market segments where CT100 addresses a specific need. In IoT device security, device OEMs building connected industrial sensors and smart meters are evaluating CT100 for root-of-trust applications where the current alternative is either a discrete secure element from NXP or STMicroelectronics at higher cost, or a software-only security implementation that lacks hardware-level tamper resistance. In banking terminals, the hardware security module market in India is currently served primarily by imported devices, and a domestically designed secure processor could qualify for preference under government digital payments infrastructure programmes. In defence, the DRDO contract provides a funded development path for the defence-grade variant of CT100 with environmental and reliability specifications beyond the commercial CT100's standard specification. A successful first silicon bring-up will enable customer sampling to begin within three months, with first commercial orders targeted for Q2 2027.
