AMD Bengaluru GPU Tape-Out Signals India's Arrival in Frontier Chip Design
AMD has announced that its Bengaluru engineering centre has completed the tape-out of a next-generation RDNA GPU compute unit cluster, a milestone that represents the first time a complete GPU core complex has been submitted to silicon from an AMD team based in India. Tape-out, the submission of a completed chip design to the foundry for wafer fabrication, is the culmination of months of design, verification, and physical implementation work, and a tape-out owned by the Bengaluru team means that Indian engineers are responsible for the correctness and completeness of a chip design that will be manufactured in billions of transistors and evaluated against AMD's performance and power specifications. The milestone reflects the progression of AMD's India engineering organisation from supporting roles in earlier GPU generations to full ownership of product sub-systems in the current one, and it is a significant marker in India's development as a country where frontier semiconductor design, not just design support, is performed.
RDNA Architecture and the Compute Unit Cluster
AMD's RDNA GPU architecture, used in Radeon gaming GPUs and in the graphics subsystems of AMD's integrated APUs, is organised around compute units, each of which contains the shader processors, texture units, and local data share memory that perform the parallel floating-point computations at the heart of GPU workloads. A compute unit cluster groups multiple compute units with shared cache and interconnect infrastructure, and the cluster design determines a significant portion of the GPU's performance per unit area and power. Designing the RDNA cluster requires expertise in microarchitecture, digital circuit design, power distribution, clock distribution, timing closure, and physical implementation at leading-edge process nodes, covering the full range of digital VLSI design disciplines. The Bengaluru team's ownership of the cluster tape-out demonstrates that AMD's India engineers have developed this full-stack design capability, not just proficiency in selected sub-tasks.
CDNA AI Accelerator Contribution
Beyond the RDNA GPU design, the AMD Bengaluru team contributes to the CDNA AI accelerator architecture that powers AMD's Instinct data centre GPU products, which compete with NVIDIA's H100 and B200 in the AI training and inference accelerator market. The CDNA programme at Bengaluru involves verification of compute engine designs, development of the high-bandwidth memory interface subsystems that connect the GPU compute fabric to HBM memory stacks, and power management logic that optimises the accelerator's performance-per-watt ratio across the dynamic workloads of AI training. While the CDNA programme contributions are at the subsystem level rather than full-system ownership, they are in the most technically demanding and commercially important area of AMD's product portfolio, and they demonstrate the Bengaluru team's capability to contribute to the highest-stakes semiconductor design programmes in the industry.
India as AMD's Largest Global Engineering Site
AMD's Bengaluru centre, which crossed 4,000 engineers in 2026, has been designated by AMD's leadership as the company's largest global engineering site outside the United States. This designation reflects both the scale of the India team and the depth of its programme ownership, which has grown from design verification support in the early years to full tape-out leadership in the current period. AMD has committed to continuing to grow the Bengaluru site and to extending the range of programmes with India team ownership as the site's capabilities mature. The tape-out milestone, announced publicly by AMD, is unusual in its specificity and reflects AMD's desire to signal to the semiconductor industry and to the Indian engineering talent market that Bengaluru is a site where the most ambitious semiconductor design work happens, not a support office for the company's US design teams.
